1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory system, which are particularly preferable for use in a pseudo-SRAM (Static Random Access Memory).
2. Description of the Related Art
A pseudo-SRAM which is one of semiconductor memory devices is a memory of which memory cells for storing data are constituted of the same cells as those of a DRAM (Dynamic Random Access Memory), and of which external interface has compatibility with a SRAM. The pseudo-SRAM has the characteristics of the DRAM of having larger capacity at lower bit cost as compared with the SRAM, and has equal usability to the SRAM, and thus realizes an increase in capacity and facilitation of system design. For example, a low-power (low power consumption) pseudo-SRAM is used as a memory (RAM) for a cellular phone.
FIG. 1 is a block diagram showing a constitution of a conventional pseudo-SRAM 101. The pseudo-SRAM 101 has a memory cell array 102, an array control circuit 103, a refresh control circuit 104, a chip control circuit 105, an address decoder 106, a data signal control circuit 107 and an interface circuit 108.
The memory cell array 102 is constituted of a plurality of memory cells disposed in an array form with respect to a row direction and a column direction. Each memory cell is a 1T-1C type (one transistor and one capacitor type) memory cell as in the DRAM as described above. The array control circuit 103 performs a data read operation, a data write operation and a refresh operation for the memory cells in the memory cell array 102.
The refresh control circuit 104 outputs a request for a refresh operation for holding the data stored in the memory cells in accordance with a timer value included inside.
The chip control circuit 105 decodes a command (external command) CMD from an outside, which is supplied via the interface circuit 108, and outputs a control signal based on the decoded result and the refresh request from the refresh control circuit 104 to the array control signal 103. The command CMD is constituted of a chip enable signal /CE, an address valid signal /ADV, an output enable signal /OE and a write enable signal /WE (“/” which is affixed to the reference symbol of each signal indicates that the signal is of negative logic).
The chip control circuit 105 performs arbitration (arbitration processing) of the access request (data read/write) by the command CMD and the refresh request. In this arbitration, the request precedently generated is processed in preference.
The address decoder 106 decodes an address signal ADD from an outside, which is supplied via the interface circuit 108, and outputs the decoded result to the array control circuit 103.
The data signal control circuit 107 controls transmission and reception of data signals between the inside and the outside of the memory in the read operations and the write operations performed in accordance with the external commands.
A clock signal CLK, which synchronizes the input and output timings of the command CMD and a data signal DQ, is inputted into the interface circuit 108 from an outside, and is supplied to each functional section in the pseudo-SRAM 101.
FIG. 2 is a timing chart explaining the operation (data read operation) in the conventional pseudo-SRAM. In FIG. 2, a “core operation” is a selection operation for the memory cell array 102, in other words, the operation executed for the memory cell array 102 by the array control circuit 103. A “Peri operation” is the operation of peripheral circuits of the memory cell array 102 (array control circuit 103) such as the chip control circuit 105 and the data signal control circuit 107.
First, at a time T51, the chip enable signal /CE which brings the device (pseudo-SRAM) into an operational state, the address valid signal /ADV indicating that the address signal ADD is valid, and the output enable signal /OE change to “L”. The chip control circuit 105 decodes this command CMD and determines that the access request from the outside is the data read operation RD (A). The address decoder 106 takes in the address signal ADD and decodes it.
However, if the refresh request from the refresh control circuit 104 generates before the time T51 when the access request from the outside is received, the refresh operation REF is executed in the memory cell array 102 (time T52). From a time T53 when the refresh operation REF is finished, the data read operation RD (A) is executed in the memory cell array 102, and data (1A), (2A) and (3A) of the memory cells corresponding to the decoded result in the address decoder 106 are sequentially read and outputted as the data signal DQ.
When the chip enable signal /CE changes to “H” at a time T54, the chip control circuit 105 instructs termination of the data read operation RD (A) to the array control circuit 103. By this, the data read operation RD (A) executed in the memory cell array 102 is finished (time T55).
When the chip enable signal /CE and the address valid signal /ADV change to “L” at the time T55, the chip control circuit 105 decodes the command CMD at this time, and determines that the access request from the outside is a data read operation RD (B). The address decoder 106 takes in the address signal ADD and decodes it.
At a time T56 when a refresh entry term TREN elapses from the time T55, the data read operation RD (B) is executed in the memory cell array 102, and data (1B), (2B), (3B), (4B) and (5B) are outputted as the data signal DQ. The refresh entry term TREN is always set between the data read/write operation according to the access request from the outside so that the refresh operation can be executed in the memory cell array 102 when the refresh request generates.
Thereafter, as in the data read operation RD (A), the chip enable signal /CE changes to “H” at a time T57, and thereby the data read operation RD (B) executed in the memory cell array 102 is finished (time T58).
FIG. 3 is a timing chart explaining an operation (data write operation) in the conventional pseudo-SRAM. The data write operation shown in FIG. 3 differs from the data read operation shown in FIG. 2 only in the respects that the write enable signal /WE is made “L” and the output enable signal /OE is kept at “H” and that the data (1A) to (3A) and (1B) to (5B) supplied as the data signal DQ are written into the memory cells, and in the other respects, it is the same as the data read operation shown in FIG. 2 (times T61 to T68 correspond to the times T51 to T58 respectively). Therefore, the explanation of the data write operation will be omitted.
As shown in FIGS. 2 and 3, the data read operation, the data write operation and the like are performed in the conventional pseudo-SRAM.
In recent years, a large-capacity and real time data communication related to video data and the like comes to be performed, and the operation at higher speed is demanded of the pseudo-SRAM which is used as the memory of a data communication apparatus including a cellular phone or the like.
[Patent Document 1] Japanese Patent Application Laid-open No. Hei 11-16346
[Patent Document 2] International Publication No. WO 98/56004
However, in the conventional pseudo-SRAM, the refresh entry term TREN is always provided as shown in FIGS. 2 and 3, and therefore, the access time related to the access request from the outside is specified so as to include the latency on the assumption of the case in which the refresh request precedently occurs, which is the worst case. A series of operations from reception of the access request (command) from the outside to input and output of the data is executed so that the series of operations corresponding to the next access request is started after a series of operations corresponding to an access request, namely, only the processing according to one access request is always performed.
As a method for enhancing the speed of the operation (access) in the pseudo-SRAM, the method of decreasing the access time from the outside by shortening the latency as shown in FIG. 4A can be considered. However, if the latency is shortened, a time interval TC between the data read/write operations by the access request from the outside is shortened, and there arises the fear that the term corresponding to the refresh entry term TREN cannot be ensured. Namely, when the latency is shortened, the refresh operation cannot be executed between the data read/write operations by the access request from the outside if the refresh request occurs, and there arises the fear that the data stored in the memory cells disappear.
As another method for enhancing the speed of the operation in the pseudo-SRAM, the method of multiplexing the access requests from the outside as shown in FIG. 4B is considered. However, if the data read operation RD (B) is requested when the data read operation RD (A) is being executed as shown in a time T91 in FIG. 4B, the address signal ADD related to the data read operation RD (B) is taken in and decoded at this point of time. Therefore, the decoded result in the address decoder 106 changes, and different memory cells are selected. Accordingly, when the data read operation RD (B) is requested during execution of the data read operation RD (A), the access request from the outside cannot be recognized accurately, and it cannot be guaranteed that accurate data is outputted from this point of time (data (3A) in the example shown in FIG. 4B). The same is equally true of the data write operation.